3-Channel Stand Alone Bridge Chip for Multi-Camera Applications

Interfaces:
– Two 2‑lane MIPI receiver for video input
– One of the MIPI receivers can be divided into dual 1‑lane MIPI receivers
– One 4‑lane MIPI receiver for video input
– One 4‑lane MIPI transmitter for video output
– Up to 1 MHz SCCB with 13 MHz ~ 26 MHz input clock
– Two sets of SCCB master
– One set of SCCB master and slave
– Four sensor frame rate control pin
– Five general purpose IO (GPIO) pins
– UART and SPI interfaces

On-chip PLLs:
– System PLL – input clock frequency ranges from 13 MHz to 26 MHz
– MIPI speed – 5x or 10x of system clock for RAW, 4x or 8x of system clock for YUV

Image signal processor (ISP):
– AEC/AGC/AWB
– Two ISPs, one for each input video stream
– 2592 x 1944 max resolution
– Max frame rate: 24 fps at 5MP, 30 fps at 4MP, 60 fps at 1080p, 120 fps at 720p
– Lens shading correction (LENC)
– Auto exposure and gain control
– Auto white balance
– Defect pixel correction
– Auto contrast enhancement
– Gamma correction
– YCbCr422 process

SCCB:
– Two sets of SCCB masters to control multiple sensors
– One SCCB master/slave to take the commands from host controller
– 7‑bit SCCB slave device ID is fixed to 0x44 (0x88 for write, and 0x89 for read)
– 7‑bit SCCB slave device ID is fixed to 0x42 (0x84 for write, and 0x85 for read)
– Supports SCCB clock 100 kHz and 400 kHz and 1 MHz

Data format:
– Input: RAW 8/10/12-bit, YUV422
– Output: RAW 8/10/12-bit, YUV422

Microcontroller:
– 32‑bit microcontroller running at the system clock
– 64 KByte program memory, 32 KB ROM

Power supply:
– 1.8V for IO voltage (e.g., PADVDD18), 1.8V for analog voltage (e.g., M*AVDD)
– Internal regulator generates 1.2V C*VDD12 from PADVDD18 for the digital core circuit
– Hardware standby mode initiated by pulling PWDN high, whole system halts and input clock is gated
– Software standby mode initiated by register