Interfaces:
– Four one-lane MIPI receiver for video input
– Can combine to dual 2-lane video input
– One channel two-lane MIPI transmitter for video output
– Up to 400 kHz SCCB with 13 MHz ~ 26 MHz input clock
– Three general purpose IO (GPIO)
– One open drain output CMD_RDY

On-chip PLLs:
– System PLL – input clock frequency ranges from 13 MHz to 26 MHz
– MIPI speed – 5x or 10x of system clock for raw, 4x or 8x of system clock for YUV

Image signal processor (ISP)
– AEC/AGC/AWB
– Two ISPs, one for each input video stream
– Max resolution: 1280 x 800
– Max frame rate: 60 fps at 720p, 120 fps at VGA, 240 fps at QVGA
– Defect pixel correction (DPC)
– Lens shading correction (LENC)

SCCB:
– One SCCB master to control sensors
– One SCCB slave to take the commands from host controller
– 7-bit SCCB slave device ID is fixed to 0x35 (0x6A for write, and 0x6B for read)
– Supports SCCB clock 100 kHz and 400 kHz

Data format:
– Input: raw
– Output: raw 8/10-bit, YUV422

Microcontroller:
– 8-bit microcontroller running at the system clock
– 16 KByte program memory

Power supply:
– 1.8V for DOVDD, 2.8V for MIPI and PLL analog
– Internal regulator generates 1.2V DVDD from DOVDD for the digital core circuit
– Hardware standby mode: initiated by pulling PWDN high, whole system halts and input clock is gated
– Software standby mode: initiated by register, whole system except the SCCB slave block halt